1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method and for example to a method for manufacturing a semiconductor device having a gate electrode and a resistive interconnection.
2. Description of the Background Art
In a semiconductor substrate having an element isolation film of the background art, a resistive interconnection having a relatively high resistance value (e.g. a resistance value of about several hundred to several thousand ohms) is formed on the element isolation film and a gate electrode is formed on the semiconductor substrate in isolation from the resistive interconnection.
In the semiconductor device thus structured, impurity ions are implanted into the resistive interconnection to control its resistance value, and impurity ions are also implanted into the semiconductor substrate to form diffusion layers in areas on both sides of the gate electrode. Subsequently a heat treatment is applied to activate the diffusion layers.
Related prior arts include the following (for example, refer to the First to Third Patent Documents): Japanese Patent Application Laid-Open Nos. 2-128465 (1990), 2-228065 (1990), and 2000-216254.
However, in the method above, the heat treatment causes out-diffusion of ions from the resistive interconnection. This makes it impossible to precisely control the resistance value of the resistive interconnection.
Also, while First Patent Document discloses a technique in which an oxide film is formed on the resistive interconnection after formation of transistors, the oxide film formation involves an additional heat treatment, which varies the characteristics of the transistors and makes it impossible to provide highly precise transistors.
Also, even when the resistive interconnection is formed after the formation of the gate electrode, the formation of the resistive interconnection involves an additional heat treatment, which may vary the transistor characteristics.